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Develop and execute strategic account plans to drive design wins and revenue growth at assigned accounts/territory (CSP in Seattle with focus on MS and Amazon) Serve as a “trusted advisor” to engineer
Validation: Develop and execute validation plans and test cases for DDR4 and DDR5 memory systems, ensuring compliance with industry standards. Validate memory component functionality, compatibility, a
UVM SystemVerilog 测试与质量 芯片 / 半导体
Be knowledgeable in DDR5 DIMM system level verification and PMIC IP verification; Collaborate closely with component testing verification teams across our global sites; Interface with other engineerin
Verilog Python Linux 研发（未细分） 芯片 / 半导体
Individual contributor to the design in a collaborative team environment Design various logic & state machines in SystemVerilog/Verilog RTL Develop and debug RTL, using industry-standard simulation an
EDA Linux Verilog 研发（未细分） 芯片 / 半导体
Work in a cross functional team environment, leading and contributing to the PMIC product development; Full custom analog design of blocks such as PLLs, oscillators, bandgap references, LDOs, Buck / B